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fully accurate 12-/14-/16-bit v out dac spi interface 2.7 v to 5.5 v in a tssop pac preliminary technical data ad5024/44/64 rev. prd information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2007 analog devices, inc. all rights reserved. features low power quad 16/14/12 bit dac, 1lsb inl pin compatible and performance upgrade to ad5666 individual and common voltage reference pin options rail-to-rail operation 2.7 v to 5.5 v power supply power-on reset to zero scale or midscale 3 power-down functions per channel power down low glitch on power up hardware ldac with ldac override function clr function to programmable code sdo daisy-chaining option 14/16-lead tssop applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagrams figure 1.AD5064 functional equi valent and pin compatible with ad5666 figure 2. AD5064/44/24 general description the ad5024/44/64 are low power, quad 12-/14-/16-bit buffered voltage-out dacs offering relative accuracy specs of 1 lsb inl with individual and common reference pin options and can operate from a single 2.7 v to 5.5 v supply. the ad5024/44/64 parts also offer a differential accuracy specification of 1 lsb. the parts use a versatile 3-wire, low power schmitt trigger serial interface that operates at clock rates up to 50 mhz and is compatible with standard spi?, qspi?, microwire?, and dsp interface standards. a reference buffer is also provided on- chip. the ad5024/44/64 incorporates a power-on reset circuit that ensures the dac output powers up to zero scale or midscale and remains there until a valid write takes place to the device. the ad5024/44/64 contain a power-down feature that reduces the current consumption of the device to typically 400 na at 5 v and provides software selectable output loads while in power-down mode. total unadjusted error for the parts is <2 mv. product highlights 1. quad channel available in 14/16-lead tssop package. 2. 14-lead tssop option provides a pin compatable and performance upgrade to the ad5666 with individual and common voltage reference pin options. 3. 16 bit accurate, 1 lsb inl. 4. low glitch on power-up. 5. high speed serial interface with clock speeds up to 50 mhz. 6. reset to known output voltage (zero scale or midscale). table 1. related devices part no. description ad5666 quad,16-bit buffered d/a,16 lsb inl, tssop ad5066 quad,16-bit unbuffered d/a,1 lsb inl, tssop ad5065/45/25 dual 16-bit nano dac, 1 lsb inl, tssop ad5063/62 16-bit nano dac, 1 lsb inl, msop ad5061 16-/14bit nano dac, 4 lsb inl, sot-23 ad5060/40 16-/14bit nano dac, 1 lsb inl, sot-23
ad5024/44/64 preliminary technical data rev. prd| page 2 of 29
preliminary technical data ad5024/44/64 rev. prd | page 3 of 29 specifications v dd = 2.7 v to 5.5 v, r l = 2 k to gnd, c l = 200 pf to gnd, 2.2v v refin . v dd unless otherwise specified. all specifications t min to t max , unless otherwise noted. table 2. a grade 1 2 b grade 1 parameter min typ max min typ max unit conditions/comments static performance 3 resolution 16 16 bits AD5064 14 ad5044 12 ad5024 relative accuracy 0.5 4 0.5 1 lsb AD5064 t a = -40c to +105c 0.5 0.5 1.5 AD5064 t a = -40c to +125c 0.5 1 lsb ad5044 t a = -40c to +105c 0.5 1.5 ad5044 t a = -40c to +125c 0.5 1 lsb ad5024 t a = -40c to +105c 0.5 1.5 ad5024 t a = -40c to +125c differential nonlinearity 1 1 lsb total unadjusted error tue 0.2 2 0.2 2 mv AD5064 t a = -40c to +105c 0.2 2 0.2 2 mv AD5064 t a = -40c to +125c offset error 1 9 1 9 mv all 0s loaded to dac register offset error drift 2 2 v/c full-scale error ?0.2 ?1 ?0.2 ?1 % fsr all 1s loaded to dac register gain error 1 1 % fsr gain temperature coefficient 2.5 2.5 ppm of fsr/c dc power supply rejection ratio C80 C80 db v dd 10% dc crosstalk 0.5 0.5 lsb due to single-channel full-scale output change, r l = 2 k to gnd or v dd 0.5 0.5 lsb/m a due to load current change 0.5 0.5 lsb due to powering down (per channel) output characteristics 4 output voltage range 0 v dd 0 v dd v capacitive load stability 1 1 pf r l = 5 k, r l =100k and r l = dc output impedance (normal mode) 0.5 0.5 dc output impedance dac in power down mode (output connected to 100k network) 100 k output impedance tolerance 20 (output connected to 1k network) 1 k output impedance tolerance 400 short-circuit current 60 60 ma dac = full scale, o/p shorted to gnd 45 45 ma dac = zero scale, o/p shorted to v dd power-up time 4.5 4.5 s coming out of power-down mode v dd = 5 v dc psrr -92 -92 db v dd 10%, dac = full scale wideband sfdr -67 -67 db output frequency = 10khz reference inputs reference input range 2.2 v dd 2.2 v dd v reference current 30 50 30 50 a per dac channel reference input impedance 120 120 k individual reference option
ad5024/44/64 preliminary technical data rev. prd| page 4 of 29 a grade 1 2 b grade 1 parameter min typ max min typ max unit conditions/comments 30 30 k common reference option logic inputs 4 input current 5 3 3 a all digital inputs input low voltage, v inl 0.8 0.8 v v dd = 5 v input high voltage, v inh 2 2 v v dd = 5 v pin capacitance 4 4 pf logic outputs (sdo) 4 output low voltage, v ol 0.4 0.4 v i sink = 2 ma output high voltage, v oh v dd ? 1 v dd ? 1 i source = 2 ma high impedance leakage current 0.25 0.25 a high impedance output capacitance 2 2 pf power requirements v dd 2.7 5.5 2.7 5.5 v all digital inputs at 0 or v dd dac active, excludes load current i dd (normal mode) 6 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 5 6 5 6 ma i dd (all power-down modes) 7 v dd = 4.5 v to 5.5 v 0.4 1 0.4 1 a v ih = v dd and v il = gnd 1 temperature range is ?40c to +105c, typi cal at 25c. 2 a grade offered in AD5064 only 3 linearity calculated using a reduced code rang e of 512 to 65,024. output unloaded. 4 guaranteed by design and characterization; not production tested. 5 total current flowing into all pins. 6 . interface inactive. all dacs active. dac outputs unloaded 7 . all four dacs powered down
preliminary technical data ad5024/44/64 rev. prd | page 5 of 29 ac characteristics v dd = 2.7 v to 5.5 v, r l = 2 k to gnd, c l = 200 pf to gnd, v refin = v dd . all specifications t min to t max , unless otherwise noted. table 3. parameter 1 , 2 min typ max unit conditions/comments 3 output voltage settling time 5 s ? to ? scale settling to 1 lsb,r l = 5k single channel update including dac calibration sequence output voltage settling time 14 s ? to ? scale settling to 1 lsb,r l = 5k all channel update including dac calibration sequence slew rate 1.5 v/s digital-to-analog glitch impulse 4 nv-s 1 lsb change around major carry reference feedthrough ?90 db v ref = 2 v 0.1 v p-p, frequency = 10 hz to 20 mhz sdo feedthrough 3 nv-s daisy-chain mode; sdo load is 10 pf digital feedthrough 0.1 nv-s digital crosstalk 0.5 nv-s analog crosstalk 6 nv-s dac-to-dac crosstalk 6.5 nv-s ac crosstalk 6 nv-s ac psrr tbd multiplying bandwidth 340 khz v ref = 2 v 0.2 v p-p total harmonic distortion ?80 db v ref = 2 v 0.1 v p-p, frequency = 10 khz output noise spectral density 64 nv/hz dac code = 0x8400, 1 khz 60 nv/hz dac code = 0x8400, 10 khz output noise 6 v p-p 0.1 hz to 10 hz 1 guaranteed by design and characterization; not production tested. 2 see the terminology section. 3 temperature range is ?40c to + 105c, typi cal at 25c.
ad5024/44/64 preliminary technical data rev. prd| page 6 of 29 timing characteristics all input signals are specified with tr = tf = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 4 and figure 6 . v dd = 2.7 v to 5.5 v. all specifications t min to t max , unless otherwise noted. table 4. limit at t min , t max parameter v dd = 2.7 v to 5.5 v unit conditions/comments t 1 1 20 ns min sclk cycle time t 2 10 ns min sclk high time t 3 10 ns min sclk low time t 4 16.5 ns min sync to sclk falling edge set-up time t 5 5 ns min data set-up time t 6 5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 1.9 us min minimum sync high time (single channel update) t 8 10.5 ns min minimum sync high time ( all channel update) t 9 16.5 ns min sync rising edge to sclk fall ignore t 10 0 ns min sclk falling edge to sync fall ignore t 11 20 ns min ldac pulse width low t 12 20 ns min sclk falling edge to ldac rising edge t 13 10 ns min clr pulse width low t 14 10 ns min sclk falling edge to ldac falling edge t 15 10.6 us min clr pulse activation time t 16 2 , 3 22 ns max sclk rising edge to sdo valid t 17 3 5 ns min sclk falling edge to sync rising edge t 18 3 8 ns min sync rising edge to sclk rising edge t 19 3 0 ns min sync rising edge to ldac falling edge 1 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v. guaranteed by design and characterization; not production tested. 2 measured with the load circuit of figure 18. t 16 determines the maximum sclk fr equency in daisy-chain mode. 3 daisy-chain mode only. 2ma i ol 2ma i oh v oh (min) to output pin c l 50pf 0 5298-002 figure 3. load circuit for digital output (sdo) timing specifications
preliminary technical data ad5024/44/64 rev. prd | page 7 of 29 05858-002 t 4 t 3 sclk sync din t 1 t 2 t 5 t 6 t 7 t 8 db23 t 9 t 10 t 11 t 12 ldac 1 ldac 2 t 14 1 asynchronous ldac update mode. 2 synchronous ldac update mode. clr t 13 t 15 v out db0 figure 4. serial write operation t 7 t 4 t 3 t 9 t 16 t 19 t 17 t 18 t 11 t 8 32 64 scl sync din sdo ldac undefined input word for dac n input word for dac n input word for dac n 1 t 1 t 2 db0 db31 db0 db31 db31 db0 05298-004 figure 5. daisy-chain timing diagram
ad5024/44/64 preliminary technical data rev. prd| page 8 of 29 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v v out to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +125c storage temperature range ?65c to +150c junction temperature (t j max ) +150c tssop package power dissipation (t j max ? t a )/ ja ja thermal impedance 150.4c/w reflow soldering peak temperature snpb 240c pb free 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ad5024/44/64 rev. prd | page 9 of 29 pin configuration and fu nction descriptions 0000-006 1 2 3 4 5 6 7 AD5064 v dd v out a por v out c 14 13 12 11 10 9 8 din gnd v out b sdo v out d sclk top view (not to scale) ldac clr sync vref figure 6. 14-lead tssop (ru-14) table 6. pin function descriptions pin no. mnemonic description 1 ldac pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows all dac outputs to simultaneo usly update. alternatively, this pin can be tied permanently low. 2 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the input shift register. data is transferred in on the falling edges of the next 32 clocks. if sync is taken high before the 32nd falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 3 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 v out a analog output voltage from dac a. the outp ut amplifier has rail-to-rail operation. 5 v out c analog output voltage from dac c. the outp ut amplifier has rail-to-rail operation. 6 por power-on reset pin. tying this pin to gnd powe rs up the part to 0 v. tying this pin to v dd powers up the part to midscale. 7 v refin this is a common pin for reference input for daca,b,c and d. 8 sdo serial data output. can be used fo r daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. the serial data is transferred on the rising edge of sclk and is valid on the falling edge of the clock. 9 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the input register and the dac register are updated with the data contained in the clr code registerzero, midscale, or full scale. default setting clears the output to 0 v. 10 v out d analog output voltage from dac d. the outp ut amplifier has rail-to-rail operation. 11 v out b analog output voltage from dac b. the outp ut amplifier has rail-to-rail operation. 12 gnd ground reference point for all circuitry on the part. 13 din serial data input. this device has a 32-bit shift regist er. data is clocked into the register on the falling edge of the serial clock input. 14 sclk serial clock input. data is clocked in to the input shift register on the fall ing edge of the serial clock input. data can be transferred at rates of up to 50 mhz.
ad5024/44/64 preliminary technical data rev. prd| page 10 of 29 0000-007 1 2 3 4 5 6 7 AD5064/44/24 15 14 13 12 11 10 9 top view (not to scale) 8 gnd v out b v out d k din scl clr vrefd vrefb 16 v dd v out a r v out c ldac po c syn vrefc vrefa figure 7. 16-lead tssop (ru-16) table 7. pin function descriptions pin no. mnemonic description 1 ldac pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows all dac outputs to simultaneo usly update. alternatively, this pin can be tied permanently low. 2 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the input shift register. data is transferred in on the falling edges of the next 32 clocks. if sync is taken high before the 32nd falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 3 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 v ref b dac b reference input .this is the reference voltage input pin for dac b. 5 v ref a dac a reference input .this is the reference voltage input pin for dac a. 6 v out a analog output voltage from dac a. the outp ut amplifier has rail-to-rail operation. 7 v out c analog output voltage from dac c. the outp ut amplifier has rail-to-rail operation. 8 por power-on reset pin. tying this pin to gnd powe rs up the part to 0 v. tying this pin to v dd powers up the part to midscale. 9 v ref c dac b reference input .this is the reference voltage input pin for dac c. 10 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the input register and the dac register are updated with the data contained in the clr code registerzero, midscale, or full scale. default setting clears the output to 0 v. 11 v ref d dac a reference input .this is the reference voltage input pin for dac d. 12 v out d analog output voltage from dac d. the outp ut amplifier has rail-to-rail operation. 13 v out b analog output voltage from dac b. the outp ut amplifier has rail-to-rail operation. 14 gnd ground reference point for all circuitry on the part. 15 din serial data input. this device has a 32-bit shift regist er. data is clocked into the register on the falling edge of the serial clock input. 16 sclk serial clock input. data is clocked in to the input shift register on the fall ing edge of the serial clock input. data can be transferred at rates of up to 50 mhz.
preliminary technical data ad5024/44/64 rev. prd | page 11 of 29 typical performance characteristics tbd figure 8. inl tbd figure 9. dnl tbd figure 10. tue tbd figure 11. inl vs. reference input voltag tbd figure 12. dnl vs. reference input voltage tbd figure 13. tue vs. reference input voltage
ad5024/44/64 preliminary technical data rev. prd| page 12 of 29 tbd figure 14. gain error and full-scale error vs. temperature tbd figure 15. offset error vs. temperature tbd figure 16. gain error and full-scale error vs. supply voltage tbd figure 17. zero-scale error and offset error vs. supply voltage tbd figure 18. i dd histogram v dd = 3.0 v tbd figure 19. i dd histogram v dd = 5.0 v
preliminary technical data ad5024/44/64 rev. prd | page 13 of 29 figure 20. headroom at rails vs. source and sink tbd figure 21. source and sink current capability with v dd = 3 v tbd figure 22. source and sink current capability with v dd = 5 v tbd figure 23. supply current vs. code tbd figure 24. supply current vs. temperature tbd figure 25. supply current vs. supply voltage
ad5024/44/64 preliminary technical data rev. prd| page 14 of 29 figure 26. supply current vs. logic input voltage figure 27. full-scale settling time tbd figure 28. power-on reset to 0 v tbd figure 29. power-on reset to midscale tbd figure 30. exiting po wer-down to midscale tbd figure 31. digital-to-analog glitch impulse (see figure 36 )
preliminary technical data ad5024/44/64 rev. prd | page 15 of 29 tbd figure 32. analog crosstalk tbd figure 33. dac-to -dac crosstalk tbd figure 34. 0.1 hz to 10 hz output noise plot tbd figure 35. typical supply current vs. frequency @ 5.5 v 1 tbd figure 36. digital-to-analog glitch energy tbd figure 37. noise spectral density, internal reference
ad5024/44/64 preliminary technical data rev. prd| page 16 of 29 tbd figure 38. total harmonic distortion tbd figure 39. settling time vs. capacitive load tbd figure 40. hardware clr tbd figure 41. multiplying bandwidth tbd figure 42.typical output slew rate
preliminary technical data ad5024/44/64 rev. prd | page 17 of 29 terminology relative accuracy for the dac, relative accuracy, or integral nonlinearity (inl), is a measure of the maximum deviation in lsbs from a straight line passing through the endpoints of the dac transfer function. figure 8 shows a plot of typical inl vs. code. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed mono- tonic by design. figure 9 shows a plot of typical dnl vs. code. offset error offset error is a measure of the difference between the actual v out and the ideal v out , expressed in millivolts in the linear region of the transfer function. offset error is measured on the AD5064 with code xxx loaded into the dac register. it can be negative or positive and is expressed in millivolts. zero-code error zero-code error is a measure of the output error when zero code (0x0000) is loaded into the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the AD5064, because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in millivolts. figure 17 shows a plot of typical zero-code error vs. supply. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percentage of the full-scale range. zero-code error drift zero-code error drift is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. full-scale error full-scale error is a measure of the output error when full-scale code (0xffff) is loaded into the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed as a percentage of the full-scale range. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 31 and figure 36 . dc power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in decibels. v ref is held at 2 v, and v dd is varied 10%. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac (or soft power-down and power-up) while monitoring another dac kept at midscale. it is expressed in microvolts. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in microvolts per milliamp. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (that is, ldac is high). it is expressed in decibels. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device, but is measured when the dac is not being written to ( sync held high). it is specified in nv-s and measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa.
ad5024/44/64 preliminary technical data rev. prd| page 18 of 29 digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s. analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping ldac high, and then pulsing ldac low and monitoring the output of the dac whose digital code has not changed. the area of the glitch is expressed in nv-s. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s or vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in decibels.
preliminary technical data ad5024/44/64 rev. prd | page 19 of 29 theory of operation d/a section the ad5024/44/64 are single 12-/14 and 16-bit, serial input, voltage output dacs. the parts operate from supply voltages of 2.7 v to 5.5 v. data is written to the ad5024/44/64 in a 32-bit word format via a 3-wire serial interface. the ad5024/44 and AD5064 incorporate a power-on reset circuit that ensures the dac output powers up to a known out-put state. the devices also have a software power-down mode that reduces the typical current consumption to less than 1 a. because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n refin out d vv 2 the ideal output voltage when using and internal reference is given by ? ? ? ? ? ? = n refout out d v v 2 2 where: d = decimal equivalent of the binary code that is loaded to the dac register. 0 to 65,535 for AD5064 (16 bits). n = the dac resolution. dac architecture the dac architecture of the AD5064 consists of two matched dac sections. a simplified circuit diagram is shown in figure 43 . the four msbs of the 16-bit data word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of 15 matched resistors to either gnd or v ref buffer output. the remaining 12 bits of the data word drive switches s0 to s11 of a 12-bit voltage mode r-2r ladder network. 2r 047762-027 s0 v ref 2r s1 2r s11 2r e1 2r e2 2r e15 2r v out 12-bit r-2r ladder four msbs decoded into 15 equal segments figure 44. dac ladder structure reference buffer the ad5024/44 and AD5064 operate with an external reference. depending upon the device model (see figure 6 , figure 7 and the ordering guide ), the package will either have a single common voltage reference pin that is connected to all four dacs or alternatively each dac will have a dedicated voltage reference pin. in either case the reference input pin has an input range of 2 v to v dd . this input voltage is then used to provide a buffered reference for the dac core. output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . the amplifier is capable of driving a load of 2 k in parallel with 1,000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in (tbd) and (tbd) . the slew rate is 1.5 v/s with a ? to ? scale settling time of 10 s. serial interface the ad5024/44/64 has a 3-wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards as well as most dsps. see figure 4 for a timing diagram of a typical write sequence. standalone mode the write sequence begins by bringing the sync line low. data from the din line is clocked into the 32-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 50 mhz, making the ad5024/44/64 compatible with high speed dsps. on the 32 nd falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in dac register contents and/or a change in the mode of operation. at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v in = 2 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation of the part. as is mentioned previously, however, sync must be brought high again just before the next write sequence. table 8. command definitions command c3 c2 c1 c0 description 0 0 0 0 write to input register n 0 0 0 1 update dac register n 0 0 1 0 write to input register n, update all (software ldac ) 0 0 1 1 write to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 load clear code register 0 1 1 0 load ldac register
ad5024/44/64 preliminary technical data rev. prd| page 20 of 29 0 1 1 1 reset (power-on reset) 1 0 0 0 set up dcen register 1 (daisy chain enable) 1 0 0 1 reserved 1 1 1 1 reserved table 9. address commands address (n) a3 a2 a1 a0 selected dac channel 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 1 1 1 1 all dacs 1 available in ad5024/44/ 64 16 tssop package only.
preliminary technical data ad5024/44/64 rev. prd | page 21 of 29 input shift register the ad5024/44/64 input shift register is 32 bits wide (see figure 45 ). the first four bits are dont cares. the next four bits are the command bits, c3 to c0 (see table 9 ), followed by the 4- bit dac address bits, a3 to a0 (see table 10 ) and finally the bit data-word. the data-word comprises either 12-/14 or 16-bit input code followed by 8-/6 or 4 dont care bits for the ad5024/44/64 (see figure 45 ). these data bits are transferred to the dac register on the 32 nd falling edge of sclk. sync interrupt in a normal write sequence, the sync line is kept low for at least 32 falling edges of sclk, and the dac is updated on the 32 nd falling edge. however, if sync is brought high before the 32 nd falling edge, this acts as an interrupt to the write sequence. the shift register is reset, and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see figure 48 ). 05298-025 address bits command bits c3 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x xxx db31 (msb) db0 (lsb) data bits figure 45. AD5064 input register content 05298-025 address bits command bits c3c2c1c0a3a2a1a0d13d12d11d10d9d8d7d6d5d4d3d2d1d0 xxxx x xxx db31 (m s b) db0 (lsb) data bits xx figure 46. ad5044 input register content 05298-025 address bits command bits c3c2c1c0a3a2a1a0d11d10d9d8d7d6d5d4d3d2d1d0 xxxx x xxx db31 (m s b) db0 (lsb) data bits xx xx figure 47. ad5024 input register content 05298-026 sclk din db31 db0 invalid write sequence: sync high before 32nd falling edge valid write sequence, output updates on the 32nd falling edge db31 db0 sync figure 48. sync interrupt facility
ad5024/44/64 preliminary technical data rev. prd| page 22 of 29 daisy-chaining for systems that contain several dacs, or where the user wishes to read back the dac contents for diagnostic purposes, the sdo pin (pin available in 16-lead ad5024/44/64 only see ordering guide ) can be used to daisy-chain several devices together and provide serial read-back. the daisy-chain mode is enabled through a software executable dcen command. command 1000 is reserved for this dcen function (see table 8 ). the daisy-chain mode is enabled by setting a bit (db1) in the dcen register. the default setting is standalone mode, where bit dcen = 0 . table 10 shows how the state of the bits corresponds to the mode of operation of the device. the sclk is continuously applied to the input shift register when sync is low. if more than 32 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the din input on the next dac in the chain, a multi-dac interface is constructed. each dac in the system requires 32 clock pulses; therefore, the total number of clock cycles must equal 32n, where n is the total number of devices in the chain. when the serial transfer to all devices is complete, sync is taken high. this prevents any further data from being clocked into the input shift register. if sync is taken high before 32 clocks are clocked into the part, it is considered an invalid frame and the data is discarded. the serial clock can be continuous or a gated clock. a continuous sclk source can be used only if the sync can be held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. power-on reset the ad5024/44/64 contains a power-on reset circuit that controls the output voltage during power-up. by connecting the por pin low, the ad5666 output powers up to 0 v; by connecting the por pin high, the ad5024/44/64 output powers up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. there is also a software executable reset function that resets the dac to the power-on reset code. command 0111 is reserved for this reset function (see table 8 ). any events on ldac or clr during power-on reset are ignored. power-down modes the ad5024/44/64 contains four separate modes of operation. command 0100 is reserved for the power-down function (see table 8 ). these modes are software-programmable by setting two bits, bit db9 and bit db8, in the control register(refer to table 13 ). table 12 shows how the state of the bits corresponds to the mode of operation of the device. any or all dacs (dac d to dac a) can be powered down to the selected mode by setting the corresponding four bits (db3, db2, db1, db0) to 1. see table 13 for the contents of the input shift register during power-down/ power-up operation. when both bit db9 and bit d8, in the control register are set to 0, the part works normally with its normal power consumption of tbd at 5 v. however, for the three power-down modes, the supply current falls to tbd at 5 v ( tbd at 3 v). not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power- down mode. there are three different options. the output is connected internally to gnd through either a 1 k or a 100 k resistor, or it is left open-circuited (three-state). the output stage is illustrated in figure 49 . the bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and v dd = 3 v (see figure 30 ). any combination of dacs can be powered up by setting pd1 and pd0 to 0 (normal operation). the output powers up to the value in the input register ( ldac low) or to the value in the dac register before powering down ( ldac high).
preliminary technical data ad5024/44/64 rev. prd | page 23 of 29 table 10. dcen (daisy-chain enable) register (db1) (db0) action 0 0 standalone mode (default) 1 0 dcen mode table 11. 32-bit input shift register contents for daisy-chain enable and reference set-up function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db2 to db19 db1 db0 x 1 0 0 0 x x x x x 1/0 x dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares dcen register table 12. modes of operation db9 db8 operating mode 0 0 normal operation power-down modes 0 1 1 k to gnd 1 0 100 k to gnd 1 1 three-state table 13. 32-bit input shift register contents for power-up/power-down function msb lsb db31 to db28 db27 db26 db25 db 24 db23 db22 db21 db20 db10 to db19 db9 db8 db4 to db7 db3 db2 db1 db0 x 0 1 0 0 x x x x x pd1 pd0 x dac d dac c dac b dac a dont cares command bits (c2 to c0) address bits (a3 to a0) dont cares dont cares power-down mode dont cares power-down/power-up channel selection set bit to 1 to select figure 49. output stage during power-down
ad5024/44/64 preliminary technical data rev. prd| page 24 of 29 clear code register the ad5024/44/64 has a hardware clr pin that is an asynchronous clear input. the clr input is falling edge sensitive. bringing the clr line low clears the contents of the input register and the dac registers to the data contained in the user-configurable clr register and sets the analog outputs accordingly. (see table 14 ) this function can be used in system calibration to load zero scale, midscale, or full scale to all channels together. these clear code values are user- programmable by setting two bits, bit db1 and bit db0, in the control register (see table 14 ). the default setting clears the outputs to 0 v. command 0101 is reserved for loading the clear code register (see table 8 ). the part exits clear code mode on the 32 nd falling edge of the next write to the part. if clr is activated during a write sequence, the write is aborted. the clr pulse activation timethe falling edge of clr to when the output starts to changeis typically tbd ns. however, if outside the dac linear region, it typically takes tbd ns after executing clr for the output to start changing (see figure 40 ). see table 15 for contents of the input shift register during the loading clear code register operation ldac function the outputs of all dacs can be updated simultaneously using the hardware ldac pin. synchronous ldac : after new data is read, the dac registers are updated on the falling edge of the 32 nd sclk pulse. ldac can be permanently low or pulsed as in figure 4 asynchronous ldac : the outputs are not updated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the contents of the input register. alternatively, the outputs of all dacs can be updated simultaneously using the software ldac function by writing to input register n and updating all dac registers. command 0010 is reserved for this software ldac function. an ldac register gives the user extra flexibility and control over the hardware ldac pin. this register allows the user to select which combination of channels to simultaneously update when the hardware ldac pin is executed. setting the ldac bit register to 0 for a dac channel means that this channels update is controlled by the ldac pin. if this bit is set to 1, this channel updates synchronously; that is, the dac register is updated after new data is read, regardless of the state of the ldac pin. it effectively sees the ldac pin as being tied low. (see table 16 for the ldac register mode of operation.) this flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. writing to the dac using command 0110 loads the 4-bit ldac register (db3 to db0). the default for each channel is 0; that is, the ldac pin works normally. setting the bits to 1 means the dac channel is updated regardless of the state of the ldac pin. see table 1 7 for the contents of the input shift register during the load ldac register mode of operation. power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5666 should have separate analog and digital sections. if the ad5666 is in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5666. the power supply to the ad5024/44/64 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should physically be as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and low effective series inductance (esi), such as is typical of common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board.
preliminary technical data ad5024/44/64 rev. prd | page 25 of 29 table 14. clear code register clear code register db1 db0 cr1 cr0 clears to code 0 0 0x0000 0 1 0x8000 1 0 0xffff 1 1 no operation table 15. 32-bit input shift register contents for clear code function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db2 to db19 db1 db0 x 0 1 0 1 x x x x x 1/0 1/0 dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares clear code register (cr1 to cr0) table 16. ldac overwrite definition load dac register ldac bits (db3 to db0) ldac pin ldac operation 0 1/0 determined by ldac pin 1 xdont care dac channels update, overrides the ldac pin. dac channels see ldac as 0. table 17. 32-bit input shift register contents for ldac overwrite function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db4 to db19 db3 db2 db1 db0 x 0 1 1 0 x x x x x dac d dac c dac b dac a dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares dont cares setting ldac bit to 1 override ldac pin
ad5024/44/64 preliminary technical data rev. prd| page 26 of 29 microprocessor interfacing ad5024/44/6 to black fin ? adsp-bf53x interface figure 50 shows a serial interface between the ad5024/44/64 and the black fin adsp-bf53x microprocessor. the adsp- bf53x processor family incorporates two dual-channel synchronous serial ports, sport1 and sport0, for serial and multiprocessor communications. using sport0 to connect to the ad5623r/ad5643/ad5663r, the setup for the interface is as follows: dt0pri drives the din pin of the ad5623r/ad5643/ad5663r, while tsclk0 drives the sclk of the parts. the sync is driven from tfs0. AD5064/ ad5044/ 1 adsp-bf53x 1 sync tfs0 din dtopri sclk tsclk0 1 additional pins omitted for clarity. 0000-049 ad5024 figure 50. ad5024/44/64 to black fin adsp-bf53x interface ad5024/44/64 to 68hc11/68l11 interface figure 51 shows a serial interface between the ad5024/44/64 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5024/44/64, and the mosi output drives the serial data line of the dac. AD5064/ ad5044/ 1 68hc11/68l11 1 sync pc7 sclk sck din mosi 1 additional pins omitted for clarity. 0000-050 ad5024/ figure 51. ad5024/44/64 to 68hc11/68l11 interface the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this interface are as follows: the 68hc11/68l11 is configured with its cpol bit as 0, and its cpha bit as 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/ 68l11 is configured as described previously, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the ad5024/44/64, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure. ad5024/44/64 to 80c51/80l51 interface figure 52 shows a serial interface between the ad5024/44/64 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/ 80l51 drives sclk of the ad5024/44/64, and rxd drives the serial data line of the part. the sync signal is again derived from a bit-programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5024/44/64, p3.3 is taken low. the 80c51/80l51 transmit data in 8-bit bytes only; thus, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 output the serial data in a format that has the lsb first. the ad5024/44/64 must receive data with the msb first. the 80c51/80l51 transmit routine should take this into account. AD5064/ ad5044/ 1 0000-052 ad5024 80c51/80l51 1 sync p3.3 sclk txd din rxd 1 additional pins omitted for clarity. figure 52. ad5024/44/64 to 80c512/80l51 interface ad5024/44/6 to microwire interface figure 53 shows an interface between the ad5024/44/64 and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the ad5024/44/64 on the rising edge of the sclk. microwire 1 cs sk so AD5064/ ad5044/ 1 sync din sclk 1 additional pins omitt ed for clarity. 0000-049 ad5024 figure 53. ad5024/44/64 to microwire interface
preliminary technical data ad5024/44/64 rev. prd | page 27 of 29 applications using a reference as a power supply for the ad5024/44/64 because the supply current required by the ad5024/44/64 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the parts (see figure 54 ). this is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 v or 3 v, for example, 15 v. the voltage reference outputs a steady supply voltage for the ad5024, ad5044 and AD5064. if the low dropout ref195 is used, it must supply 500 a of current to the ad5024/ ad5044 / AD5064, with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k load on the dac output) is 500 a + (5 v/5 k) = 1.5 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in a 3 ppm (15 v) error for the 1.5 ma current drawn from it. this corresponds to a 0.196 lsb error. AD5064/ ad5044/ ad5024 three-wire serial interface sync sclk din 15 v 5v v out =0vto5v v dd ref195 0000-053 figure 54. ref195 as power supply to the ad5024/44/64 bipolar operation using the ad5024/44/64 the ad5024/44/64 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 55 . the circuit gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2r1d vv dd dd o 536,65 where d represents the input code in decimal (0 to 65,535). with v dd = 5 v, r1 = r2 = 10 k, v5 536,65 10 ? ? ? ? ? ? ? = d v o this is an output voltage range of 5 v, with 0x0000 corre- sponding to a ?5 v output, and 0xffff corresponding to a +5 v output. three-wire serial interface r2 = 10k ? +5v ?5v ad820/ op295 +5v ad5024/44/64 v dd v out r1 = 10k ? 5v 0.1f 10f 0000-053 figure 55. bipolar operation with the ad5024/44/64 using the ad5024/44/64 with a galvanically isolated interface in process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that can occur in the area where the dac is functioning. i coupler? provides isolation in excess of 2.5 kv. the ad5024/44/64 uses a 3-wire serial logic interface, so the adum1300 three-channel digital isolator provides the required isolation (see figure 56 ). the power supply to the part also needs to be isolated, which is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5024/44/64. 0.1f 5v regulator gnd din sync sclk power 10f sdi sclk d a ta ad5024/44/64 v out v ob v oa v oc v dd v ic v ib v ia adum1300 0000-055 figure 56. ad5024/44/64 with a galvanically isolated interface
ad5024/44/64 preliminary technical data rev. prd| page 28 of 29 outline dimensions 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity 0.10 compliant to jedec standards mo-153-ab-1 figure 57. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 58. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters
preliminary technical data ad5024/44/64 rev. prd | page 29 of 29 ordering guide model temperature range package description package option power-on reset to code accuracy resolution AD5064bruz-1 1 ?40c to +105c 14-lead tssop ru-14 zero 1 lsb inl 16 bits AD5064bruz-1reel7 ?40c to +105c 14-lead tssop ru-14 zero 1 lsb inl 16 bits AD5064aruz-1 2 ?40c to +105c 14-lead tssop ru-14 zero 4 lsb inl 16 bits AD5064aruz-1reel7 ?40c to +105c 14-lead tssop ru-14 zero 4 lsb inl 16 bits AD5064bruz ?40c to +105c 16-lead tssop ru-16 zero 1 lsb inl 16 bits AD5064bruz-reel7 ?40c to +105c 16-lead tssop ru-16 zero 1 lsb inl 16 bits AD5064bcpz ?40c to +105c 16-lead lfcsp cp-16 zero 1 lsb inl 16 bits AD5064bcpz-reel7 1 3 ?40c to +105c 16-lead lfcsp cp-16 zero 1 lsb inl 16 bits ad5044bruz ?40c to +105c 16-lead tssop ru-16 zero 1 lsb inl 14 bits ad5044bruz-reel7 ?40c to +105c 16-lead tssop ru-16 zero 1 lsb inl 14 bits ad5044bcpz ?40c to +105c 16-lead lfcsp cp-16 zero 1 lsb inl 14 bits ad5044bcpz-reel7 ?40c to +105c 16-lead lfcsp cp-16 zero 1 lsb inl 14 bits ad5024bruz ?40c to +105c 16-lead tssop ru-16 zero 1 lsb inl 12 bits ad5024bruz-reel7 ?40c to +105c 16-lead tssop ru-16 zero 1 lsb inl 12 bits ad5024bcpz ?40c to +105c 16-lead lfcsp cp-16 zero 1 lsb inl 12 bits ad5024bcpz-reel7 ?40c to +105c 16-lead lfcsp cp-16 zero 1 lsb inl 12 bits eval-ad5066 ebz evaluation board eval-ad5066 ebz evaluation board eval-ad5066 ebz evaluation board 1 z = pb-free part. 2 z = pb-free part. 3 needs to be conf irmed by marketing ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr06803-0-6/07(prd)

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